High power supply rejection wideband Low-Dropout regulator

A 90nm 1.4-3.3V CMOS Low-Dropout regulator for noise-sensitive low-current RF blocks in mixed SoC applications is presented. It is based on a two loops topology with replica technique and an additional Gm-C filter introduced in the replica loop for high power supply rejection at both low and high frequencies. Complete PSR and stability analyses are presented. The regulator is implemented in a 90nm CMOS technology and achieves a PSR better than -60dB from 0 to 30MHz with only a 47nF external output capacitor. This architecture is highly versatile since the replica design may remain very basic. The active chip area is only 0.0088mm², making this LDO an ideal block for a locally distributed power management strategy.