Title :
12.7-times energy efficiency increase of 16-bit integer unit by power supply voltage (VDD) scaling from 1.2V to 310mV enabled by contention-less flip-flops (CLFF) and separated VDD between flip-flops and combinational logics
Author :
Fuketa, Hiroshi ; Hirairi, Koji ; Yasufuku, Tadashi ; Takamiya, Makoto ; Nomura, Masahiro ; Shinohara, Hirofumi ; Sakurai, Takayasu
Author_Institution :
Inst. of Ind. Sci., Univ. of Tokyo, Tokyo, Japan
Abstract :
Contention-less flip-flops (CLFF´s) and separated power supply voltages (VDD) between flip-flops (FF´s) and combinational logics are proposed to achieve a maximum energy efficiency operation. The proposed technologies were applied to a 16-bit integer unit (IU) for media processing in a 65-nm CMOS process. Measurement results of fabricated chips show that the proposed CLFF reduces the minimum operating voltage of IU´s by 64mV on average. By scaling VDD from 1.2V to 310mV with the proposed CLFF, the maximum energy efficiency of 1835GOPS/W and the highest energy efficiency increase of 12.7 times are achieved.
Keywords :
CMOS logic circuits; flip-flops; CLFF; CMOS process; combinational logics; contention-less flip-flops; energy efficiency; integer unit; power supply voltage scaling; size 65 nm; voltage 1.2 V to 310 mV; word length 16 bit; CMOS integrated circuits; Clocks; Energy efficiency; Flip-flops; Frequency measurement; Latches; Transistors; flip-flop; subthreshold circuit; variations;
Conference_Titel :
Low Power Electronics and Design (ISLPED) 2011 International Symposium on
Conference_Location :
Fukuoka
Print_ISBN :
978-1-61284-658-3
Electronic_ISBN :
Pending
DOI :
10.1109/ISLPED.2011.5993630
