Reduction of minimum operating voltage (VDDmin) of CMOS logic circuits with post-fabrication automatically selective charge injection

In order to reduce minimum operating voltage (V_DDmin) of CMOS logic circuits, a new method reducing the within-die random threshold (V_TH) variation of transistors by a post-fabrication automatically selective charge injection using substrate hot electrons (SHE) is proposed along with novel circuitry to utilize this. In the new circuit, switches are added to combinational logic circuits in order to turn them into latch loops. In order to reduce V_DDmin, design guides on the optimal (1) loop topology, (2) number of stages in a loop, (3) V_TH shift per charge injection, and (4) number of charge injection trials are explored through simulations. By applying the proposed scheme to 96-stage inverter chain fabricated in 65-nm CMOS, the measured reduction of V_DDmin from 94mV to 74mV is successfully demonstrated for the first time.