DocumentCode
2888473
Title
A novel technique for folding logic arrays
Author
Kannan, L.N. ; Sarma, D.
Author_Institution
Cadence Design Syst., Santa Clara, CA, USA
fYear
1991
fDate
4-8 Jan 1991
Firstpage
100
Lastpage
105
Abstract
The folding of logic arrays is a technique to reduce the area of the array by exploiting its sparsity. Since the problem is NP-complete, heuristic algorithms that yield a near optimal solution have to be employed. In this paper the array optimization problem has been studied and a method employing a combination of simulated annealing and heuristic algorithms has been developed to find a near optimal solution for both simple and multiple folding of logic arrays. The algorithms developed have been implemented in a computer program called GAMIN-SA. When compared to PLEASURE, GAMIN-SA was seen to perform as good or better with regard to quality of solution and, for the bigger PLAs (multiple folding), it was better in terms of run-time as well
Keywords
logic CAD; logic arrays; simulated annealing; GAMIN-SA; PLAs; area; array optimization problem; folding; heuristic algorithms; logic arrays; near optimal solution; run-time; simulated annealing; sparsity; Computational modeling; Computer science; Heuristic algorithms; Input variables; Logic arrays; Logic design; Optimization methods; Programmable logic arrays; Runtime; Simulated annealing;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Design, 1991. Proceedings., Fourth CSI/IEEE International Symposium on
Conference_Location
New Delhi
Print_ISBN
0-8186-2125-7
Type
conf
DOI
10.1109/ISVD.1991.185100
Filename
185100
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