Partitioning and reorganization of hierarchical circuits for DFT

To make VLSI circuits more testable, design-for-testability (DFT) and built-in self-test (BIST) techniques are often employed. These techniques typically assume a register/gate level decomposition of the overall circuit. In general, the given user hierarchy is not appropriate for embedding various testable design methodologies (TDMs). This paper describes a new canonical partitioning of a circuit into disjoint subcircuits, referred to as clouds and registers. A salient feature of this partitioning is the attempt to preserve the user hierarchy as much as possible. This enables easy identification of equivalence among various clouds of the circuit. The authors also show how this canonical partitioning can be used for three specific TDMs, namely full scan, partial scan and BILBO designs. For the case of full scan, deterministic tests are generated for one cloud in each equivalence class, and replicated for all clouds in that class. These tests are organized to form a test set for the entire circuit. Test vectors are edited to correspond to the order of flip-flops in the scan paths of the circuit. Analytical expressions for the reduction in the number of test vectors due to this canonical partitioning are derived and substantiated with experimental results