Title :
Cost performance issues of arithmetic unit design for neural accelerators
Author :
Sammut, K.M. ; Jones, S.
Author_Institution :
Dept. of Electron. & Electr. Eng., Loughborough Univ. of Technol., UK
fDate :
27 Jun- 2 Jul 1994
Abstract :
Arithmetic unit design for linear arrays is a key design issue when supporting neural networks. However, there appears to be little quantitative evidence from the study of available linear array neural accelerator architectures to justify the choice of one arithmetic structure over another. This paper reports the results of a design study assessing cost performance trade offs in arithmetic unit design for linear neural network accelerators
Keywords :
digital arithmetic; logic arrays; neural net architecture; neural nets; parallel processing; arithmetic unit design; cost performance issues; linear array neural accelerator architectures; Acceleration; Adders; Algorithm design and analysis; Arithmetic; Circuits; Clocks; Computer architecture; Costs; Linear accelerators; Neural networks;
Conference_Titel :
Neural Networks, 1994. IEEE World Congress on Computational Intelligence., 1994 IEEE International Conference on
Conference_Location :
Orlando, FL
Print_ISBN :
0-7803-1901-X
DOI :
10.1109/ICNN.1994.374823
