• DocumentCode
    2888494
  • Title

    A processor chip set on a 60K master image chip

  • Author

    Schettler, H. ; Koetzle, G.

  • Author_Institution
    IBM Laboratories, Boeblingen, Germany
  • Volume
    XXX
  • fYear
    1987
  • fDate
    0-0 Feb. 1987
  • Firstpage
    88
  • Lastpage
    89
  • Abstract
    The implementation of two processor chips using a master image design methodology, implemented in a 1μm CMOS process will be reported. Containing 800K transistors the chips produce a typical delay of 0.8ns. In a 12.7×12.7mm array the average density is 0.65 square mils / transistor.
  • Keywords
    CMOS logic circuits; Fuses; Libraries; Logic circuits; Power distribution; Read only memory; Read-write memory; Routing; Wire; Wiring;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference. Digest of Technical Papers. 1987 IEEE International
  • Conference_Location
    New York, NY, USA
  • Type

    conf

  • DOI
    10.1109/ISSCC.1987.1157151
  • Filename
    1157151
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2888494