Title :
A low-power direct digital frequency synthesizer using an analogue-sine-conversion technique
Author :
Weng, Jun-Hong ; Yang, Ching-Yuan ; Jhu, Yi-Lin
Author_Institution :
Dept. of Electr. Eng., Nat. Chung Hsing Univ., Taichung, Taiwan
Abstract :
A new approach for d irect digital frequency synthesizer (DDFS) with analogue sine conversion is presented. The proposed DDFS adopts the ROM-less architecture with linear DAC to achieve higher speed operation and lower power consumption. Fabricated by 0.18-μm CMOS process, the DDFS employs a 9-bits pipe line accumulator to provide an 8-bits amplitude resolution for the DAC circuit. At 1-GHz clock frequency, the power consumption is 50 mw at 1. 8-V power supply and the spurious free dynamic range (SFDR) is 44 dBc at the N yquist synthesized frequency. The total chip area is 0.52 mm2.
Keywords :
CMOS digital integrated circuits; analogue-digital conversion; direct digital synthesis; CMOS process; DAC circuit; DDFS; Nyquist synthesized frequency; ROM-less architecture; SFDR; analogue-sine-conversion technique; frequency 1 GHz; low-power direct digital frequency synthesizer; pipe line accumulator; power 50 mW; size 0.18 mum; voltage 1.8 V; word length 8 bit; word length 9 bit; Adders; CMOS integrated circuits; Frequency measurement; Frequency synthesizers; Power demand; Read only memory; Switches; DAC; ROM-less architecture; analogue-Sine-Conversion; direct digital frequency synthesizer (DDFS);
Conference_Titel :
Low Power Electronics and Design (ISLPED) 2011 International Symposium on
Conference_Location :
Fukuoka
Print_ISBN :
978-1-61284-658-3
Electronic_ISBN :
Pending
DOI :
10.1109/ISLPED.2011.5993635
