DocumentCode :
2888609
Title :
Power and delay aware synthesis of multi-operand adders targeting LUT-based FPGAs
Author :
Matsunaga, Taeko ; Kimura, Shinji ; Matsunaga, Yusuke
Author_Institution :
Inf. Technol. Res. Organ., Waseda Univ., Tokyo, Japan
fYear :
2011
fDate :
1-3 Aug. 2011
Firstpage :
217
Lastpage :
222
Abstract :
Recent researches have indicated that multi-operand addition on FPGAs can be efficiently realized as the architecture consisting of a compressor tree which reduces the number of operands and a carry-propagate adder like ASIC by utilizing generalized parallel counters(GPCs). This paper addresses power and delay aware synthesis of GPC-based compressor trees. Based on the observation that dynamic power would correlate to the number of GPCs and the levels of GPCs, our approach targets to minimize the maximum levels and the total number of GPCs, and an ILP-based algorithm and heuristic approaches are proposed. Several experiments targeting Altera Stratix III architecture show that the proposed approach reduced the delay by up to 20% under a slight increase in total power dissipation.
Keywords :
adders; field programmable gate arrays; integer programming; linear programming; trees (mathematics); ASIC; Altera Stratix III architecture; GPC-based compressor trees; ILP-based algorithm; LUT-based FPGA; carry-propagate adder; delay aware synthesis; generalized parallel counters; multioperand adders; power aware synthesis; power dissipation; Adders; Delay; Field programmable gate arrays; Minimization; Radiation detectors; Table lookup; Vegetation;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Low Power Electronics and Design (ISLPED) 2011 International Symposium on
Conference_Location :
Fukuoka
ISSN :
Pending
Print_ISBN :
978-1-61284-658-3
Electronic_ISBN :
Pending
Type :
conf
DOI :
10.1109/ISLPED.2011.5993639
Filename :
5993639
Link To Document :
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