DocumentCode
2888629
Title
A new test scheduling algorithm for VLSI systems
Author
Garg, Mahesh ; Basu, Anupam ; Wilson, T.C. ; Banerji, D.K. ; Majithia, J.C.
Author_Institution
Dept. of Comput. & Inf. Sci., Guelph Univ., Ont., Canada
fYear
1991
fDate
4-8 Jan 1991
Firstpage
148
Lastpage
153
Abstract
Presents a new test scheduling algorithm based on a new heuristic approach. A new concept of time zone tree has been proposed and the algorithm builds up the tree based on a heuristic cost function. The performance of the algorithm has been compared with existing algorithms and it demonstrates encouraging results
Keywords
VLSI; integrated circuit testing; scheduling; trees (mathematics); VLSI systems; heuristic approach; heuristic cost function; test scheduling algorithm; time zone tree; Clustering algorithms; Cost function; Heuristic algorithms; Information science; Partitioning algorithms; Pipeline processing; Scheduling algorithm; System testing; Tree graphs; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Design, 1991. Proceedings., Fourth CSI/IEEE International Symposium on
Conference_Location
New Delhi
Print_ISBN
0-8186-2125-7
Type
conf
DOI
10.1109/ISVD.1991.185108
Filename
185108
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