Title :
Simulator for IDEAL-implementation and environment
Author :
Parekhji, R.A. ; Venkatesh, G. ; Sherlekar, S.D. ; Biswas, S.
Author_Institution :
Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Bombay, India
Abstract :
Presents the simulation strategy for a new hardware description language, IDEAL. IDEAL supports hierarchical and modular descriptions of asynchronous and synchronous digital systems in terms of behaviours and structures. It forms the basis of the IDEAS project for VLSI CAD tools development. The simulator for IDEAL is based on the coroutine model. A design in IDEAL is simulated by appropriately scheduling coroutines corresponding to the design entities. The behavioral and structural description is translated into coroutines by compiling IDEAL data transfer and control constructs into `C´. The semantics of IDEAL constructs are discussed and the simulator implementation and supporting environment are described
Keywords :
VLSI; circuit CAD; digital simulation; logic CAD; specification languages; C language; IDEAL; VLSI CAD tools; asynchronous digital systems; coroutine model; data transfer; design entities; hardware description language; hierarchical descriptions; modular descriptions; simulation strategy; simulator implementation; supporting environment; synchronous digital systems; Clocks; Computational modeling; Design automation; Digital systems; Documentation; Government; Hardware design languages; Logic; Object oriented modeling; Very large scale integration;
Conference_Titel :
VLSI Design, 1991. Proceedings., Fourth CSI/IEEE International Symposium on
Conference_Location :
New Delhi
Print_ISBN :
0-8186-2125-7
DOI :
10.1109/ISVD.1991.185115
