Title :
Signal delay in linear leaky RC mesh/tree
Author :
Jain, Navneet K. ; Prasad, V.C. ; Bhattacharyya, A.B.
Author_Institution :
Indian Inst. of Technol., New Delhi, India
Abstract :
As chip dimensions are reduced, the performance of integrated circuits is limited by the delays associated with the interconnections. For the purpose of propagation delay estimation in digital circuits, these interconnections can be modelled by leaky RC tree/line/mesh. Signal delay in a nonleaky RC tree can be estimated by a tree algorithm. In this paper a modified tree algorithm (linear order) is presented for estimating signal delay in a leaky RC tree with nonzero initial conditions
Keywords :
delays; digital integrated circuits; trees (mathematics); chip dimensions; delays; digital circuits; interconnections; linear leaky RC mesh/tree; nonzero initial conditions; propagation delay estimation; signal delay; tree algorithm; Capacitance; Capacitors; Circuits; Delay lines; Laplace equations; Matrix decomposition; Quantum computing; Sparse matrices; Vectors; Voltage;
Conference_Titel :
VLSI Design, 1991. Proceedings., Fourth CSI/IEEE International Symposium on
Conference_Location :
New Delhi
Print_ISBN :
0-8186-2125-7
DOI :
10.1109/ISVD.1991.185116
