DocumentCode
2888835
Title
A scan-based BIST technique using pair-wise compare of identical components
Author
Nadeau-Dostie, Benoit ; Wilcox, Philip S. ; Agarwal, Vinod K.
Author_Institution
Bell-Northern Res. Ltd., Ottawa, Ont., Canada
fYear
1991
fDate
4-8 Jan 1991
Firstpage
225
Lastpage
230
Abstract
Addresses the problem of efficiently testing scannable ASICs in a board-level and system-level environment. The method makes use of a serial testability bus (ETM or IEEE 1149.1) and takes advantage of the presence of identical components on the boards. The main benefits of the method are a significant reduction in test time and test data to be stored. Results obtained for an actual system show a reduction in test time of about 20 times for a module with 50 ASICs. The extra board area required was less than 2% for all boards of the module
Keywords
application specific integrated circuits; automatic testing; built-in self test; integrated circuit testing; ASICs; board area; identical components; pair-wise compare; scan-based BIST technique; scannable ASICs; serial testability bus; test data; test time; Application specific integrated circuits; Automatic testing; Backplanes; Built-in self-test; Circuit testing; Integrated circuit testing; Printed circuits; Random access memory; System testing; Vehicles;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Design, 1991. Proceedings., Fourth CSI/IEEE International Symposium on
Conference_Location
New Delhi
Print_ISBN
0-8186-2125-7
Type
conf
DOI
10.1109/ISVD.1991.185121
Filename
185121
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