Title :
A 7.4ns CMOS 16 × 16 multiplier
Author :
Oowaki, Yukihito ; Numata, K. ; Tsuchiya, K. ; Tsuda, Kazuhiko ; Nitayama, A. ; Watanbe, S.
Author_Institution :
Toshiba VLSI Research Center, Kawasaki, Japan
Abstract :
A CMOS 16×16b multiplier with submicrometer gatelength, incorporating a modified array implementing Booth´s algorithm will be discussed. The multiplication time is 7.4ns for 3V operation, with 400mW dissipation at a 10MHz clock rate.
Keywords :
Adders; CMOS technology; Clocks; Gallium arsenide; Latches; Paper technology; Power dissipation; Semiconductor devices; Semiconductor materials; Space technology;
Conference_Titel :
Solid-State Circuits Conference. Digest of Technical Papers. 1987 IEEE International
Conference_Location :
New York, NY, USA
DOI :
10.1109/ISSCC.1987.1157168
