Title :
Defect and design error location procedure-theoretical basis
Author_Institution :
Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
Abstract :
In this paper theoretical basis for VLSI chip defect diagnosis and defect location are discussed and a simple diagnosability measure is introduced. The proposed framework can be used to evaluate quality of defect diagnosis oriented testing vectors, as well as, for the development of test generation algorithms
Keywords :
VLSI; fault location; integrated circuit testing; VLSI chip defect diagnosis; design error location procedure; diagnosability measure; test generation algorithms; testing vectors; Circuit faults; Circuit testing; Computer errors; Contamination; Digital circuits; Fault diagnosis; Fault location; Integrated circuit modeling; Semiconductor device measurement; Very large scale integration;
Conference_Titel :
VLSI Design, 1991. Proceedings., Fourth CSI/IEEE International Symposium on
Conference_Location :
New Delhi
Print_ISBN :
0-8186-2125-7
DOI :
10.1109/ISVD.1991.185124
