Defect and design error location procedure-theoretical basis

Author

Maly, Wojciech

Author_Institution

Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA

fYear

1991

fDate

4-8 Jan 1991

Firstpage

243

Lastpage

248

Abstract

In this paper theoretical basis for VLSI chip defect diagnosis and defect location are discussed and a simple diagnosability measure is introduced. The proposed framework can be used to evaluate quality of defect diagnosis oriented testing vectors, as well as, for the development of test generation algorithms

Keywords

VLSI; fault location; integrated circuit testing; VLSI chip defect diagnosis; design error location procedure; diagnosability measure; test generation algorithms; testing vectors; Circuit faults; Circuit testing; Computer errors; Contamination; Digital circuits; Fault diagnosis; Fault location; Integrated circuit modeling; Semiconductor device measurement; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Design, 1991. Proceedings., Fourth CSI/IEEE International Symposium on

Conference_Location

New Delhi

Print_ISBN

0-8186-2125-7

Type

conf

DOI

10.1109/ISVD.1991.185124

Filename

185124

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2888882