Title :
A Monte Carlo simulation environment for wear out in VLSI systems
Author :
Choi, Gwan S. ; Iyer, Ravi K. ; Patel, Janak H.
Author_Institution :
Coordinated Sci. Lab., Illinois Univ., Urbana-Champaign, IL, USA
Abstract :
The authors describe a simulation environment for reliability prediction of VLSI designs. Specifically, the effect of electromigration on the time-to-failure is investigated. The capabilities of the environment are illustrated with a case study of a microprocessor intended for control applications. The system under investigation is first simulated at the switch level and trace data on the switching activity is collected. This data is then used along with Monte Carlo simulation to model wear-out at the chip-level
Keywords :
Monte Carlo methods; VLSI; circuit analysis computing; circuit reliability; digital simulation; electromigration; failure analysis; Monte Carlo simulation environment; VLSI designs; chip-level; electromigration; model wear-out; reliability prediction; switch level; time-to-failure; Circuit optimization; Circuit simulation; Current density; Electromigration; Equations; Integrated circuit modeling; Predictive models; Stress; Switches; Very large scale integration;
Conference_Titel :
VLSI Design, 1991. Proceedings., Fourth CSI/IEEE International Symposium on
Conference_Location :
New Delhi
Print_ISBN :
0-8186-2125-7
DOI :
10.1109/ISVD.1991.185125
