Title :
Layout methods to reduce CMOS stuck-open faults and enhance testability
Author_Institution :
Siemens Research Laboratories, Munich, West Germany
Abstract :
CMOS layout rules that reduce the stuck-open faults by 30 to 40% and render the remaining detectagle with usual stuck-at test patterns, will be analyzed. The area penalty is less than 20%.
Keywords :
Automatic testing; CMOS logic circuits; Circuit faults; Circuit testing; Electrical fault detection; Fault detection; Laboratories; Logic testing; Semiconductor device modeling; Wiring;
Conference_Titel :
Solid-State Circuits Conference. Digest of Technical Papers. 1987 IEEE International
Conference_Location :
New York, NY, USA
DOI :
10.1109/ISSCC.1987.1157176
