An efficient Reed-Solomon decoder VLSI with erasure correction

A new architecture for implementing a Reed-Solomon error correction VLSI that utilizes the erasure information is developed. To reduce the number of arithmetic elements, we employed a serial expansion of the polynomials for the modified syndrome calculation, and used an overclocking scheme for fast internal operations. The Chien´s search algorithm is also modified to find the errors in the same order with the input codewords. The complexity of the proposed architecture is about 30% lower than that of the previously known implementation. Real-time RS decoders for HDTV and DVD applications have been implemented using an FPGA