A novel electrical test structure for measuring misalignment between polysilicon and active area in MOS VLSI technologies

Author

Srivastava, S. ; Kansal, Alpana ; Shekhar, Chandra

Author_Institution

Central Electron. Eng. Res. Inst., Pilani, India

fYear

1991

fDate

4-8 Jan 1991

Firstpage

290

Lastpage

292

Abstract

A novel test structure has been designed to electrically measure the misalignment between polysilicon and the active area in MOS technologies. This alignment is one of the most critical alignments in small geometry integrated circuit processing. The structure exploits the channel width change of specially designed MOS transistors resulting from the misalignment between the active area and polysilicon layers to develop a proportionate differential current sensing arrangement. A calibrating structure is used to translate the measured differential current to actual microns

Keywords

MOS integrated circuits; VLSI; integrated circuit technology; integrated circuit testing; spatial variables measurement; MOS VLSI; MOS transistors; active area; calibrating structure; channel width change; differential current sensing; electrical test structure; integrated circuit processing; layer misalignment measurement; mask alignment; polysilicon; small geometry; Area measurement; Circuit testing; Computational geometry; Current measurement; Electric variables measurement; Electronic equipment testing; Fabrication; Integrated circuit measurements; Integrated circuit technology; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Design, 1991. Proceedings., Fourth CSI/IEEE International Symposium on

Conference_Location

New Delhi

Print_ISBN

0-8186-2125-7

Type

conf

DOI

10.1109/ISVD.1991.185138

Filename

185138