Title :
A multilayered VLSI array design for multistage interconnection network
Author :
Mahapatra, Rabi N. ; Kar, Barun K.
Author_Institution :
Indian Inst. of Technol., Kharagpur, India
Abstract :
The multilayered 3D design of an indirect binary N-cube (IBNC) multistage interconnection network (MIN) is presented. The implementation of IBNC MIN in the form of a multilayered array seems to be attractive due to less conventional connections than that in its systolic implementation approach. The area and delay performance is also found to be better compared to other two methods of implementation
Keywords :
VLSI; hypercube networks; network synthesis; area-delay analysis; indirect binary N-cube; mapping algorithm; multilayered 3D design; multilayered VLSI array design; multistage interconnection network; Capacitance; Connectors; Delay effects; Joining processes; Multiprocessor interconnection networks; Performance analysis; Quantum mechanics; Switches; Systolic arrays; Very large scale integration;
Conference_Titel :
VLSI Design, 1991. Proceedings., Fourth CSI/IEEE International Symposium on
Conference_Location :
New Delhi
Print_ISBN :
0-8186-2125-7
DOI :
10.1109/ISVD.1991.185140
