Title :
A dynamically reconfigurable interconnection chip
Author :
Chin-Yuan Chin ; Wen-Tai Lin ; Juh-Ping Hwang ; Sow Chu ; Forman, G. ; Dunki-Jacobs, R. ; Karr, S. ; Mallick, J. ; Kung, H. ; Sussman, Aaron ; Hsu, F.H. ; Nishizawa, T.
Author_Institution :
General Electric Corporate Research & Development Center, Schenectady, NY, USA
Abstract :
This paper will describe a 70K transistor chip fabricated in a 1.25μm CMOS technology, with a 6.2×7.6mm die size, and featuring data synchronization, pipeline latency compensation and other computational elements.
Keywords :
Clocks; Computer interfaces; Data flow computing; Delay; Pipeline processing; Processor scheduling; Research and development; Shift registers; Synchronization; Systolic arrays;
Conference_Titel :
Solid-State Circuits Conference. Digest of Technical Papers. 1987 IEEE International
Conference_Location :
New York, NY, USA
DOI :
10.1109/ISSCC.1987.1157188
