مرکز منطقه ای اطلاع رساني علوم و فناوري - 1991 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers (91CH3026-2)

Keywords :

VLSI; built-in self test; circuit analysis computing; circuit layout CAD; circuit reliability; logic CAD; optimisation; scheduling; analog circuit synthesis; analog simulation; asynchronous circuit synthesis; automatic test pattern generation; built-in self-test; cell routing; combinational synthesis; controller synthesis; design for testability; diagnostics; encoding algorithms; exact algorithms; false path problem; fault simulation; fault synthesis; field-programmable gate arrays; finite state machine synthesis; framework directions; high-level layout verification; interconnect simulation; layout synthesis; logic synthesis; manufacturability; memory utilization; module generation; numerical algorithms; parallel routing; performance driven routing; performance optimization; physical partitioning; placement; real-world framework applications; reliability; scan design; scheduling; sequential synthesis; sequential verification; testability analysis; timing analysis; transistor level layout; transistor-level optimization; verification algorithms;