Title :
On clustering for minimum delay/ara
Author :
Murgai, R. ; Brayton, R.K. ; Sangiovanni-Vincentelli, A.
Author_Institution :
Dept. of EECS, California Univ., Berkeley, CA, USA
Abstract :
The authors address the problem of clustering a circuit for minimizing its delay, subject to capacity constraints on the clusters. They present an algorithm for combinational circuits and give sufficient conditions under which it is optimum. In addition, they address the problem of minimizing the number of clusters and nodes without increasing the maximum delay found by the algorithm. Finally, they extend the clustering algorithm to minimize the clock cycle of a sequential synchronous circuit.<>
Keywords :
circuit layout CAD; combinatorial circuits; integrated logic circuits; minimisation of switching nets; sequential circuits; area minimisation; capacity constraints; circuit clustering; clock cycle minimisation; cluster minimisation; clustering algorithm; combinational circuits; delay minimisation; node minimisation; sequential synchronous circuit; sufficient conditions; Clocks; Clustering algorithms; Costs; Degradation; Delay effects; Integrated circuit interconnections; Joining processes; Logic design; Sequential circuits; Sufficient conditions;
Conference_Titel :
Computer-Aided Design, 1991. ICCAD-91. Digest of Technical Papers., 1991 IEEE International Conference on
Conference_Location :
Santa Clara, CA, USA
Print_ISBN :
0-8186-2157-5
DOI :
10.1109/ICCAD.1991.185176
