Automatic synthesis of time-stationary controllers for pipelined data paths

The authors present an approach for automatically synthesizing a time-stationary control scheme for a given pipelined data path. They have developed an efficient method of producing a control specification for the data path. A highly optimized FSM (finite state machine) controller implementation is obtained by partitioning so as to minimize the total controller area. The FSM controller is implemented using either PLAs or standard cells. The present approach has been compared to published work on FSM generation and optimization, and the results indicate large savings in total controller area.<>