Delta-Sigma Analog-to-Digital Conversion via Time-Mode Signal Processing

Author

Taillefer, Christopher S. ; Roberts, Gordon W.

Author_Institution

McGill Univ., Montreal, Que.

fYear

2007

fDate

27-30 May 2007

Firstpage

13

Lastpage

16

Abstract

A new architecture and signal processing methodology is proposed to implement a first-order single-bit delta-sigma (DeltaSigma) analog-to-digital converter (ADC). The proposed design converts an analog input voltage into a time-difference variable and performs the DeltaSigma signal processing in the time-mode. This offers an incredibly compact and low-power ADC solution while thriving in a low-voltage CMOS environment. The proposed design was fabricated in a standard 0.18-mum CMOS process occupying a silicon area of 15-mum times 25-mum and consumes 475-muW of power. Experimental results reveal that the design can provide a 7-bit resolution at a sampling rate of 140-MHz and input bandwidth of 400-kHz.

Keywords

CMOS integrated circuits; low-power electronics; sigma-delta modulation; signal processing; 0.18 micron; 140 MHz; 15 micron; 25 micron; 400 kHz; 475 muW; 7 bit; CMOS process; delta-sigma analog-to-digital conversion; time-difference variable; time-mode signal processing; Analog-digital conversion; CMOS technology; Circuits; Electronic mail; Frequency; Signal design; Signal processing; Signal sampling; Silicon; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2007. ISCAS 2007. IEEE International Symposium on

Conference_Location

New Orleans, LA

Print_ISBN

1-4244-0920-9

Electronic_ISBN

1-4244-0921-7

Type

conf

DOI

10.1109/ISCAS.2007.378131

Filename

4252559