Title :
RITUAL: a performance driven placement algorithm for small cell ICs
Author :
Srinivasan, A. ; Chaudhary, K. ; Kuh, E.S.
Author_Institution :
Dept. of EECS, California Univ., Berkeley, CA, USA
Abstract :
An efficient algorithm, RITUAL (residual iterative technique for updating all Lagrange multipliers), for obtaining a placement of cell-based ICs subject to performance constraints is described. Using sophisticated mathematical techniques, one is able to solve large problems quickly and effectively. The algorithm is very simple and elegant, making it easy to implement. In addition, it yields very good results, as is shown on a set of real examples. The algorithm was tested on the ISCAS set of logic benchmark examples using parameters for 1 mu m CMOS technology. On average , there is a 25% improvement in the wire delay for these examples compared to TimberWolf-5.6 with a small impact on the chip area.<>
Keywords :
CMOS integrated circuits; circuit layout CAD; computational complexity; iterative methods; CMOS technology; ISCAS set; Lagrange multipliers; RITUAL; TimberWolf-5.6; chip area; logic benchmark examples; performance constraints; performance driven placement algorithm; residual iterative technique; small cell ICs; wire delay; Delay; Laboratories; Lagrangian functions; Mathematical model; Pins; Simulated annealing; Sparse matrices; Symmetric matrices; Timing; Wire;
Conference_Titel :
Computer-Aided Design, 1991. ICCAD-91. Digest of Technical Papers., 1991 IEEE International Conference on
Conference_Location :
Santa Clara, CA, USA
Print_ISBN :
0-8186-2157-5
DOI :
10.1109/ICCAD.1991.185188
