DocumentCode :
2889397
Title :
Wafer packing for full mask exposure fabrication
Author :
Wu, C.-T. ; Lim, A. ; Du, D.
Author_Institution :
Dept. of Comput. Sci., Minnesota Univ., Minneapolis, MN, USA
fYear :
1991
fDate :
11-14 Nov. 1991
Firstpage :
52
Lastpage :
55
Abstract :
The authors formulate and classify the various models of the wafer packing problem for the full mask exposure technique. Since the wafer packing problem is NP-hard, the authors propose a good heuristic for it. Their experiments, on real test data, indicate that this heuristic is very effective as it provides considerable cost reduction when compared with the traditional way of producing chips.<>
Keywords :
circuit layout CAD; computational complexity; integrated circuit technology; NP-hard; full mask exposure fabrication; wafer packing; Application specific integrated circuits; Computer science; Costs; Design automation; Fabrication; Foundries; Manufacturing; Packaging; Semiconductor device modeling; Testing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Computer-Aided Design, 1991. ICCAD-91. Digest of Technical Papers., 1991 IEEE International Conference on
Conference_Location :
Santa Clara, CA, USA
Print_ISBN :
0-8186-2157-5
Type :
conf
DOI :
10.1109/ICCAD.1991.185189
Filename :
185189
Link To Document :
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