Title :
A 100ns 16-point CCD cosine transform processor
Author :
Chiang, Ann-Shyn ; Bennett, P. ; Kosicki, B. ; Mountain, R. ; Lincoln, G. ; Reinold, J.
Author_Institution :
MIT, Lincoln Laboratory, Lexington, MA, USA
Abstract :
A CCD based on the vector matrix product algorithm, that has been implemented using 256 fixed weight four-quadrant multipliers will be described. 1.5 billion operations/s 40dB dynamic range and 1% accuracy have been demonstrated at a 3.3 MHz clock rate. The chip size is 4mm square and it dissipates 720mW.
Keywords :
Capacitance; Charge coupled devices; Digital filters; Discrete cosine transforms; Ducts; Equations; Fourier transforms; Kernel; Solid state circuits; Transversal filters;
Conference_Titel :
Solid-State Circuits Conference. Digest of Technical Papers. 1987 IEEE International
Conference_Location :
New York, NY, USA
DOI :
10.1109/ISSCC.1987.1157203
