• DocumentCode
    2889476
  • Title

    A 100ns 16-point CCD cosine transform processor

  • Author

    Chiang, Ann-Shyn ; Bennett, P. ; Kosicki, B. ; Mountain, R. ; Lincoln, G. ; Reinold, J.

  • Author_Institution
    MIT, Lincoln Laboratory, Lexington, MA, USA
  • Volume
    XXX
  • fYear
    1987
  • fDate
    0-0 Feb. 1987
  • Firstpage
    306
  • Lastpage
    307
  • Abstract
    A CCD based on the vector matrix product algorithm, that has been implemented using 256 fixed weight four-quadrant multipliers will be described. 1.5 billion operations/s 40dB dynamic range and 1% accuracy have been demonstrated at a 3.3 MHz clock rate. The chip size is 4mm square and it dissipates 720mW.
  • Keywords
    Capacitance; Charge coupled devices; Digital filters; Discrete cosine transforms; Ducts; Equations; Fourier transforms; Kernel; Solid state circuits; Transversal filters;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference. Digest of Technical Papers. 1987 IEEE International
  • Conference_Location
    New York, NY, USA
  • Type

    conf

  • DOI
    10.1109/ISSCC.1987.1157203
  • Filename
    1157203
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2889476