An improved dynamic register array concept for high-performance RISC processors

To avoid RISC processors accessing the external memory, an increased number of processor registers is desirable. However, sophisticated concepts are needed for the handling of large amounts of registers. Multi Windows are an improved version of Threaded Windows, the first dynamic register array concept. Both utilize dynamic register allocation for handling a very large number of general purpose registers. This concept enables fast context switches and a short interrupt latency, which makes it suitable for real time systems. In Multi Windows, the data structures were simplified and improved. Exception routines are less complex and faster. Both concepts are discussed in this article