DocumentCode
2889666
Title
A 32b microprocessor with on-chip 2Kbyte instruction cache
Author
Horowitz, Mark ; Hennessy, John ; Chow, Peter ; Gulak, P. ; Acken, J. ; Agarwal, Abhishek ; Chorng-Yeung Chu ; McFarling, S. ; Przybylski, S. ; Richardson, S. ; Salz, A. ; Simoni, Renato ; Stark, Dylan ; Steenkiste, Peter ; Tjiang, S. ; Wing, Matthew
Author_Institution
Stanford University Center for Integrated Systems, Stanford, CA, USA
Volume
XXX
fYear
1987
fDate
0-0 Feb. 1987
Firstpage
30
Lastpage
31
Abstract
A Reduced Instruction Set Computer with a 5-stage pipeline implemented with 150K transistors on an 8mm×8.5mm chip in a 2μm, 2 layer metal CMOS process, will be reported. At operational frequency of 20MHz, a 12MIPS performance has been achieved.
Keywords
Automata; Fabrication; Microprocessors;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference. Digest of Technical Papers. 1987 IEEE International
Conference_Location
New York, NY, USA
Type
conf
DOI
10.1109/ISSCC.1987.1157215
Filename
1157215
Link To Document