Title :
A 65ns CMOS DRAM with a twisted driveline sense amplifier
Author :
Shimohigashi, K. ; Kimura, K. ; Sakai, Y. ; Tanaka, H. ; Yagi, K. ; Ishihara, M. ; Miyazawa, K. ; Shimizu, S. ; Murata, J.
Author_Institution :
Hitachi Central Research Laboratory, Tokyo, Japan
Abstract :
A 4Mb DRAM, measuring 6.38×17.38mm2, using a double-well CMOS technology with a design rule of 0.8μm, will be reported. A twisted driveline sense amplifier and a multiple-phase drive sense circuit serves to enhance speed and reduce peak power supply current.
Keywords :
Bonding; CMOS technology; Design automation; Logic testing; Power supplies; Pulse amplifiers; Pulse circuits; Random access memory; Size control; Space vector pulse width modulation;
Conference_Titel :
Solid-State Circuits Conference. Digest of Technical Papers. 1987 IEEE International
Conference_Location :
New York, NY, USA
DOI :
10.1109/ISSCC.1987.1157218
