FPGA Implementation of RLS Adaptive Filter Using Dichotomous Coordinate Descent Iterations

In this paper, we present an FPGA implementation of a Recursive Least Squares adaptive filtering algorithm based on dichotomous coordinate descent iterations. The algorithm is simple for finite precision implementation, requires small chip resources, and exhibits numerical stability. For arbitrary regressors (as in antenna array beamforming), the proposed implementation allows significant increase in the weight update rate compared to implementations based on QR decomposition; for 9 and 32-element arrays, the update rates are as high as 162 kHz and 31 kHz, respectively. For 16-tap and 64-tap transversal filters, the proposed implementation provides the weight update rate 207 kHz and 76 kHz, respectively.