Title :
A Self-Biased Operational Transconductance Amplifier in 0.18 micron 3D SOI-CMOS
Author :
Christen, Jennifer Blain ; Andreou, Andreas G.
Author_Institution :
Electr. & Comput. Eng., Johns Hopkins Univ., Baltimore, MD
Abstract :
We report on the design fabrication and testing of a wide range transconductance amplifier fabricated in the 0.18 mum MIT Lincoln Labs 3D SOI-CMOS process. The amplifier is designed to operate in subthreshold and employs self-biased cascode transistors to minimize the bias lines transversing the 3 tiers in the technology
Keywords :
CMOS analogue integrated circuits; operational amplifiers; silicon-on-insulator; 0.18 micron; 3D SOI-CMOS process; bias lines; operational transconductance amplifier; self-biased cascode transistors; CMOS technology; Circuits; Costs; Fabrication; Insulation; Noise figure; Operational amplifiers; Silicon on insulator technology; Substrates; Transconductance;
Conference_Titel :
Circuits and Systems, 2007. ISCAS 2007. IEEE International Symposium on
Conference_Location :
New Orleans, LA
Print_ISBN :
1-4244-0920-9
Electronic_ISBN :
1-4244-0921-7
DOI :
10.1109/ISCAS.2007.378240
