Energy-efficient soft error-tolerant digital signal processing

Author

Shim, Byonghyo ; Shanbhag, Naresh R. ; Lee, Seok-Jun

Author_Institution

Dept. of Electr. & Comput. Eng., Illinois Univ., Urbana, IL, USA

Volume

2

fYear

2003

fDate

9-12 Nov. 2003

Firstpage

1493

Abstract

In this paper, we present energy-efficient soft error (SE)-tolerant techniques for digital signal processing (DSP) systems. The proposed technique, referred to as algorithmic soft error-tolerance (ASET), employs an low-complexity estimator of a main DSP block to guarantee reliability in presence of soft errors either in the MDSP or the estimator. For FIR filtering, it is shown that the proposed technique provides robustness to soft error rates of up to P_er=10^-2 in single-event upset (SEU). It is also shown that the proposed techniques provide 40%∼61% savings in power dissipation over that achieved via triple modula redundancy (TMR) when the desired signal-to-noise ratio SNR_des=25∼35 dB.

Keywords

FIR filters; digital signal processing chips; redundancy; FIR filtering; SEU; algorithmic soft error-tolerance; digital signal processing; energy-efficient soft error-tolerant; low-complexity estimator; power dissipation; signal-to-noise ratio; single-event upset; soft error rates; triple modula redundancy; Digital signal processing; Energy efficiency; Error analysis; Filtering; Finite impulse response filter; Power dissipation; Redundancy; Robustness; Signal processing algorithms; Single event upset;

fLanguage

English

Publisher

ieee

Conference_Titel

Signals, Systems and Computers, 2004. Conference Record of the Thirty-Seventh Asilomar Conference on

Print_ISBN

0-7803-8104-1

Type

conf

DOI

10.1109/ACSSC.2003.1292234

Filename

1292234