Hierarchical analyzer for VLSI power supply networks based on a new reduction method

Author

Yoshitome, Takeshi

Author_Institution

NTT LSI Lab., Kanagawa, Japan

fYear

1991

fDate

11-14 Nov. 1991

Firstpage

298

Lastpage

301

Abstract

The author presents an algorithm for hierarchical analysis of VLSI power supply networks. The algorithms utilizes the design hierarchy and is independent of network topology. Networks in each block are recursively reduced to equivalent and small circuits in a bottom-up manner, and node voltages in the network are calculated in a top-down manner. This makes it possible to decrease the size of the matrix to be solved and to reduce the execution time. Using the prototype program XPOWER, the power lines of excess current density and voltage drop are fed back quickly to the chip floor plan designer. XPOWER reduces the matrix size to be solved from 1/10 to 1/40 and its execution is about six times faster than with the flat method for the tested examples.<>

Keywords

VLSI; circuit analysis computing; circuit layout CAD; equivalent circuits; power integrated circuits; power supplies to apparatus; VLSI power supply networks; XPOWER; chip floor plan designer; excess current density; hierarchical analysis; network topology; power distribution analyzer; power lines; reduction method; voltage drop; Algorithm design and analysis; Circuit simulation; Equations; Large scale integration; Network topology; Power distribution; Power supplies; Switches; Very large scale integration; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer-Aided Design, 1991. ICCAD-91. Digest of Technical Papers., 1991 IEEE International Conference on

Conference_Location

Santa Clara, CA, USA

Print_ISBN

0-8186-2157-5

Type

conf

DOI

10.1109/ICCAD.1991.185258

Filename

185258