DocumentCode :
2890455
Title :
A DEM Scheme for I/Q Mismatch Compensation in Multi-Bit CT ΔΣ Modulator
Author :
Ko, Chi-Tung ; Pun, Kong-Pang
Author_Institution :
Dept. of Electron. Eng., Chinese Univ. of Hong Kong, Kowloon
fYear :
2007
fDate :
27-30 May 2007
Firstpage :
245
Lastpage :
248
Abstract :
A new dynamic element matching (DEM) technique is proposed to reduce the combined problem of non-linearity within the multi-bit digital-to-analog converters (DAC) and I/Q mismatches in the feedback paths of quadrature delta-sigma (ΔΣ) modulators. Under this scheme, the non-linearity effect of I and Q DACs is suppressed by data-weighted averaging (DWA) individually. At the same time, the two DACs are swapped according to the element selection pointers of DWA. Consequently, the image is restrained by this time-interleaved swapping. The overhead of this scheme is minimal. Extensive MATLAB simulations were performed to evaluate the performance of this scheme. With a 3rd order, 64 oversampling ratio quadrature delta-sigma modulator, this scheme shows 10dB and 25dB improvement in signal-to-noise-plus-distortion ratio (SNDR) and image rejection ratio (IRR) respectively for the case of 2-bit ΔΣ modulator.
Keywords :
delta-sigma modulation; DEM scheme; I/Q mismatch compensation; data-weighted averaging; dynamic element matching technique; element selection pointers; feedback paths; multibit CT ΔΣ modulator; multibit digital-to-analog converters; quadrature delta-sigma modulators; time-interleaved swapping; Computed tomography; Delta modulation; Digital modulation; Digital-analog conversion; Dynamic range; Feedback; Hardware; MATLAB; Monolithic integrated circuits; Performance evaluation;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems, 2007. ISCAS 2007. IEEE International Symposium on
Conference_Location :
New Orleans, LA
Print_ISBN :
1-4244-0920-9
Electronic_ISBN :
1-4244-0921-7
Type :
conf
DOI :
10.1109/ISCAS.2007.378322
Filename :
4252617
Link To Document :
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