DocumentCode
2890473
Title
Synthesis of hazard-free asynchronous circuits from graphical specifications
Author
Moon, C.W. ; Stephan, P.R. ; Brayton, R.K.
Author_Institution
Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
fYear
1991
fDate
11-14 Nov. 1991
Firstpage
322
Lastpage
325
Abstract
The authors propose some syntactic and semantic extensions to a graphical specification called the signal transition graph (STG). They allow controlled-choice places to have fanout transitions of input signals and arbitrary Boolean expressions can be used as edge labels. They also allow one STG marking to represent more than one state. These extensions allow for a more natural and compact specification of asynchronous behavior. It is also shown that syntactic constraints on STGs are not sufficient to guarantee hazard-free implementations, and techniques are presented to synthesize hazard-free SOP, (sum of products) implementations under both SIC (single input change) and MIC (multiple input change) conditions. The synthesized circuits are speed-independent. They are hazard-free, independently of the gate delay variations, assuming that the circuit operates in fundamental mode.<>
Keywords
Petri nets; logic CAD; asynchronous behavior; controlled-choice places; edge labels; fanout transitions; gate delay variations; graphical specifications; hazard free logic synthesis; hazard-free SOP; hazard-free asynchronous circuits; multiple input change; semantic extensions; signal transition graph; single input change; sum of products; Asynchronous circuits; Circuit synthesis; Clocks; Concurrent computing; Delay; Formal specifications; Hazards; Moon; Signal synthesis; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer-Aided Design, 1991. ICCAD-91. Digest of Technical Papers., 1991 IEEE International Conference on
Conference_Location
Santa Clara, CA, USA
Print_ISBN
0-8186-2157-5
Type
conf
DOI
10.1109/ICCAD.1991.185265
Filename
185265
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