New reliability mechanisms in memory design for sub-22nm technologies

Author

Aymerich, N. ; Asenov, A. ; Brown, A. ; Canal, R. ; Cheng, B. ; Figueras, J. ; Gonzalez, A. ; Herrero, E. ; Markov, S. ; Miranda, M. ; Pouyan, P. ; Ramirez, T. ; Rubio, A. ; Vatajelu, I. ; Vera, X. ; Wang, X. ; Zuber, P.

Author_Institution

Univ. Politec. de Catalunya, Barcelona, Spain

fYear

2011

fDate

13-15 July 2011

Firstpage

111

Lastpage

114

Abstract

The TRAMS (Terascale Reliable Adaptive MEMORY Systems) project addresses in an evolutionary way the ultimate CMOS scaling technologies and paves the way for revolutionary, most promising beyond-CMOS technologies. In this abstract we show the significant variability levels of future 18 and 13nm device bulk-CMOS technologies as well as its dramatic effect on the yield of memory cells, and what kind of circuit solution would be required to maintain the current yield level. Later, we discuss the impact of errors at the system level, and different approaches at system level to adapt the heterogeneous systems to user´s requirements.

Keywords

CMOS memory circuits; integrated circuit design; integrated circuit reliability; TRAMS; bulk-CMOS technology; memory cells; memory design; reliability mechanisms; size 13 nm; size 18 nm; size 22 nm; terascale reliable adaptive memory systems; CMOS integrated circuits; CMOS technology; Integrated circuit reliability; Random access memory; Redundancy; Semiconductor process modeling; DRAM; SRAM; bulk-CMOS technology; sub-22nm technology nodes;

fLanguage

English

Publisher

ieee

Conference_Titel

On-Line Testing Symposium (IOLTS), 2011 IEEE 17th International

Conference_Location

Athens

Print_ISBN

978-1-4577-1053-7

Type

conf

DOI

10.1109/IOLTS.2011.5993820

Filename

5993820