DocumentCode :
2890940
Title :
Fault Tolerance Analysis of NoC Architectures
Author :
Lehtonen, Teijo ; Liljeberg, Pasi ; Plosila, Juha
Author_Institution :
Turku Centre for Comput. Sci.
fYear :
2007
fDate :
27-30 May 2007
Firstpage :
361
Lastpage :
364
Abstract :
The paper presents an approach for analyzing and improving fault tolerance aspects in NoC architectures. This is a necessary step to be taken in order to implement reliable systems in future nanoscale technologies. Several NoC architectures and the router structures as well as the network interface needed for them are presented and compared for their fault tolerance, area and performance. The results indicate that a network structure built from simple 3-port routers provides better fault tolerance than a structure based on more complex multiport routers, and that the area overhead can be kept moderate
Keywords :
fault tolerance; nanotechnology; network interfaces; network-on-chip; NoC architectures; complex multiport routers; fault tolerance analysis; nanoscale technologies; network interface; reliable systems; router structures; Circuit faults; Clocks; Delay; Fault tolerance; Information analysis; Network interfaces; Network-on-a-chip; Power system reliability; Routing; Throughput;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems, 2007. ISCAS 2007. IEEE International Symposium on
Conference_Location :
New Orleans, LA
Print_ISBN :
1-4244-0920-9
Electronic_ISBN :
1-4244-0921-7
Type :
conf
DOI :
10.1109/ISCAS.2007.378464
Filename :
4252646
Link To Document :
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