DocumentCode
2891049
Title
Probabilistic design verification
Author
Jain, J. ; Bitner, J. ; Fussell, D.S. ; Abraham, J.A.
Author_Institution
Comput. Eng. Res. Center, Texas Univ., Austin, TX, USA
fYear
1991
fDate
11-14 Nov. 1991
Firstpage
468
Lastpage
471
Abstract
The authors present a novel method for verifying the equivalence of two Boolean functions. Each function is hashed to an integer code by assigning random integer values to the input variables and evaluating its integer-valued representation. The equivalence of two functions can be verified with a very low probability of error. The probability of error can be exponentially decreased by making multiple runs. Results indicate significant time and space advantages for this method over deterministic techniques. Some functions known to require space (and time) exponential in the number of input variables for deterministic verification require only polynomial resources using the proposed technique.<>
Keywords
Boolean functions; logic CAD; logic testing; Boolean functions; deterministic verification; equivalence; integer code; integer-valued representation; polynomial resources; probability of error; random integer values; Arithmetic; Boolean functions; Circuit testing; Digital systems; Hydrogen; Input variables; Jacobian matrices; Logic design; Polynomials; Test pattern generators;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer-Aided Design, 1991. ICCAD-91. Digest of Technical Papers., 1991 IEEE International Conference on
Conference_Location
Santa Clara, CA, USA
Print_ISBN
0-8186-2157-5
Type
conf
DOI
10.1109/ICCAD.1991.185306
Filename
185306
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