Fast Fair Crossbar Scheduler for On-chip Router

This paper proposed a scheduling algorithm for a low-cost crossbar switch design in on-chip packet-switched micro-network. The scheduling algorithm is based on a distributed arbitration scheme over crossbar fabric. Each input port is designed with a mask circuit which can provide fair arbitration. As a result, our scheduler has lower power consumption because it does not need to toggle each node frequently. Experimental results show that designs utilizing our approach can reduce scheduling delay and hardware costs more than 43% and 49% respectively, as compared to those of the popular round robin algorithm. Based on the proposed scheme for 8-input scheduling circuit design, the critical delay is 0.98 ns and the power consumption is 98 muW with 50% traffic load at 100 MHz grant signal frequency in TSMC 0.18 mum technology