A systematic approach for designing testable VLSI circuits

A systematic approach has been developed to provide designers with a set of testable versions for a given design, ranging from the minimal test time solution to the minimal area overhead solution. The designer thus has the flexibility to make the necessary tradeoff between area overhead and test time depending on the constraints of the design under consideration. By employing an expert selection developed previously, the system can be extended to operate as an intelligent BIST (built-in self-test) design advisor. Experiments have been performed on several circuits generated by MABAL, a high-level synthesis tool, to demonstrate the performance of this approach.<>