Area and Throughput Aware Comparator Networks Optimization for Parallel Data Processing on FPGA

As hardware synthesis tries to go behavioral, system designers tend to neglect low level optimizations, e.g., retiming or resources reuse. However, complex architectures such as highly parallel sorter cores cannot be directly packed into standard devices by the electronic design automation (EDA) tools and often needs fundamental rethinking. Therefore this paper resumes a cost study of the hardware realization of a recurrent parameterizable N-sorter based on Batcher´s bitonic algorithm and shows how to recombine different network sizes by preserving data throughput. With the time complexity of the original bitonic sorter, the recurrent architecture yields a lower area complexity by reducing the communication within the network and minimizes the cost in terms of hardware resources. Furthermore, the validity domain of internal architectural parameter combinations demonstrate the existence of an optimal area-throughput trade-off for very large scale integration (VLSI) models based on field programmable gate array (FPGA) synthesis, as well as a full scalability of the highly parallel sorting scheme