Application of Boolean unification to combinational logic synthesis

Author

Fujita, M. ; Tamiya, Y. ; Kukimoto, Y. ; Chen, K.-C.

Author_Institution

Fujitsu Laboratories Ltd., Kawasaki, Japan

fYear

1991

fDate

11-14 Nov. 1991

Firstpage

510

Lastpage

513

Abstract

The authors present various applications of Boolean unification to combinational logic synthesis. Three topics of combinational logic synthesis are discussed: redesign, multilevel logic minimization, and minimization of Boolean relations. All of these problems can be uniformly formalized as Boolean unification problems. Experimental results are also reported.<>

Keywords

Boolean functions; combinatorial circuits; logic CAD; Boolean unification; combinational logic synthesis; minimization of Boolean relations; multilevel logic minimization; redesign; Boolean functions; Design automation; Equations; Integrated circuit synthesis; Laboratories; Logic circuits; Logic design; Logic programming; Minimization; Space exploration;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer-Aided Design, 1991. ICCAD-91. Digest of Technical Papers., 1991 IEEE International Conference on

Conference_Location

Santa Clara, CA, USA

Print_ISBN

0-8186-2157-5

Type

conf

DOI

10.1109/ICCAD.1991.185318

Filename

185318

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2891225