Analysis and Performance Evaluation of a Digital Carrier Synchronizer for Modem Applications

Digital communication systems such as modulation-demodulation and M-PSK require the use of carrier synchronization in phase and frequency. This work addresses the implementation and analysis of a digital carrier synchronizer (DCS), which is a phase-locked loop (PLL), realized using digital circuits. This novel methodology highlights implementation promises towards some of the critical issues associated with the design of its analog counterpart, usually known as PLL. The principle function of this DCS is heavily dependent on the numerically controlled oscillator (NCO) and the loop filter (LF). There are various methods to implement NCOs and LFs that are used in the architectural model of DCS. This paper examines the performance of two different NCOs and LFs realization in DCS for modem (modulator-demodulator) application. The methods presented are look up table (LUT) and Xilinx ROM based NCO in one hand, and 1st order and 2nd order based LF. Each has its own merits and de-merits. The paper also developed a mathematical model of DCS for stability analysis. Furthermore, the authors analyzed the performance of this two implementations based on three performance metrics i.e. stability, locking-time and tracking range. From the analysis, Xilinx ROM based NCO with 2nd order LF performs better and are more suited for modem´s DCS.