• DocumentCode
    2891335
  • Title

    PARIS: a parallel pattern fault simulator for synchronous sequential circuits

  • Author

    Gouders, N. ; Kaibel, R.

  • Author_Institution
    Dept. of Data Process., Duisburg Univ., Germany
  • fYear
    1991
  • fDate
    11-14 Nov. 1991
  • Firstpage
    542
  • Lastpage
    545
  • Abstract
    The authors describe PARIS, a parallel-pattern fault simulator for synchronous sequential circuits. PARIS is based on the well-known approach of parallel pattern single fault propagation for combinational circuits and features several new techniques. Every single pattern packet is simulated by an iterative, event-driven method. Heuristic look-ahead of signal values minimizes the number of events that must be tracked. Clever circuit partitioning prevents multiple evaluation of the feedback free parts of the circuit, thus reducing the required simulation effort. Experiments show that PARIS runs at a substantially higher asymptotic speed compared with a state-of-the-art fault simulator for synchronous sequential circuits.<>
  • Keywords
    circuit analysis computing; fault location; logic CAD; sequential circuits; PARIS; circuit partitioning; combinational circuits; event-driven method; feedback free parts; heuristic look-ahead; parallel pattern fault simulator; parallel pattern single fault propagation; synchronous sequential circuits; Circuit faults; Circuit simulation; Circuit testing; Combinational circuits; Computational modeling; Data processing; Feedback circuits; Information systems; Logic; Sequential circuits;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Computer-Aided Design, 1991. ICCAD-91. Digest of Technical Papers., 1991 IEEE International Conference on
  • Conference_Location
    Santa Clara, CA, USA
  • Print_ISBN
    0-8186-2157-5
  • Type

    conf

  • DOI
    10.1109/ICCAD.1991.185327
  • Filename
    185327