Title :
Improved logic synthesis algorithms for table look up architectures
Author :
Murgai, R. ; Shenoy, N. ; Brayton, R.K. ; Sangiovanni-Vincentelli, A.
Author_Institution :
Dept. of EECS, California Univ., Berkeley, CA, USA
Abstract :
The authors address the problem of synthesis for a popular class of programmable gate array architecture-the table look-up architectures. These use lookup table memories to implement logic functions. The authors present improved techniques for minimizing the number of table look up blocks used to implement a combinational circuit. On average, the results obtained on a set of benchmarks are 15-29% better than results obtained by previous approaches.<>
Keywords :
combinatorial circuits; logic CAD; logic arrays; logic testing; table lookup; benchmarks; combinational circuit; logic functions; logic synthesis algorithms; lookup table memories; programmable gate array architecture; table look up architectures; Boolean functions; Circuit synthesis; Combinational circuits; Electronics packaging; Kernel; Logic functions; Programmable logic arrays; Prototypes; Table lookup; Wiring;
Conference_Titel :
Computer-Aided Design, 1991. ICCAD-91. Digest of Technical Papers., 1991 IEEE International Conference on
Conference_Location :
Santa Clara, CA, USA
Print_ISBN :
0-8186-2157-5
DOI :
10.1109/ICCAD.1991.185333
