Title :
Performance directed synthesis for table look up programmable gate arrays
Author :
Murgai, R. ; Shenoy, N. ; Brayton, R.K. ; Sangiovanni-Vincentelli, A.
Author_Institution :
Dept. of EECS, California Univ., Berkeley, CA, USA
Abstract :
The authors address the problem of delay optimization for programmable gate arrays. The main considerations are the number of levels in the circuit and the wiring delay. The authors propose a two-phase approach: the first phase involves delay optimizations during logic synthesis before placement, while the second uses logic resynthesis in the case of a timing-driven placement technique. Results and comparisons on benchmarks are presented.<>
Keywords :
circuit layout CAD; logic CAD; logic arrays; logic testing; table lookup; benchmarks; delay optimization; logic synthesis; performance directed synthesis; table look up programmable gate arrays; timing-driven placement; two-phase approach; wiring delay; Automation; Boolean functions; Circuit synthesis; Delay; Design optimization; Electronics packaging; Integrated circuit interconnections; Logic design; Prototypes; Wiring;
Conference_Titel :
Computer-Aided Design, 1991. ICCAD-91. Digest of Technical Papers., 1991 IEEE International Conference on
Conference_Location :
Santa Clara, CA, USA
Print_ISBN :
0-8186-2157-5
DOI :
10.1109/ICCAD.1991.185335
