The nature of defect size distributions in semiconductor processes

The combination of a small static random access memory (SRAM) and a test element group (TEG) has been shown to be an effective yield monitor for VLSI. Defects at all process levels are easily isolated, detected, and characterized through bit mapping and visual inspection. This not only provides an effective means for defect control at all process levels but also provides a unique opportunity to study the defect size distribution as a function of process and level. Defect size distributions have been measured for various process levels using a 1.25-μm CMOS SRAM/TEG yield monitor. These data have been analyzed with nonlinear regression techniques and show that the best-fit model for the defect distribution is bimodal and not a simple inverse power law, as is usually thought. The nature of the bimodal distribution has been examined on a level-by-level basis as well as on a sublevel basis in terms of specific process operation. Evaluated in this manner, the resulting defect distribution is clearly shown to be highly dependent on the facility, process, and processing equipment. Near best-fit models with simple inverse power laws show smaller power law defect distributions than are generally presented in the literature. The implications of these results with regard to yield modeling for product and technology projections are discussed