A Low-Complexity High-Speed Clock Generator for Dynamic Frequency Scaling of FPGA and Standard-Cell Based Designs

In this paper, the authors propose two high-speed variable rate clock generator circuits that can synthesize frequencies which are fractional multiples of an input clock. The designs can switch between frequencies in a glitch-free manner, within a single clock cycle. In response to an N-phase reference clock, the first circuit can generate a clock of up to N times the reference frequency, whereas the second solution can generate up to N/2 times that frequency. The available synthesized frequencies are given by f_refmiddotN/M , where M can be any integer greater than or equal to 1, depending on the circuit. The solutions were coded in VHDL, synthesized, placed and routed in TSMC´s 180nm CMOS technology. Simulations using the extracted layout show that the proposed designs can operate with a reference frequency of up to 400MHz, yielding a maximum output clock of 4times the reference, or 1.6GHz. The designs were also validated with an implementation on Xilinx´s Spartan 3 FPGA device.